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Node / ReticulumProjects / RNode_Firmware.git / commits / 5531120


Commit 5531120e2f16c5839efdfc56a987b9aeab20f780

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Parents : f50095f
Author : Adam Novak <interfect@gmail.com>
Date : 2022-02-21T15:26:14-05:00

Drop wayward semicolon

Changes

1 files changed, 6 insertions(+), 3 deletions(-)

M LoRa.cpp +6 -3

Diff

diff --git a/LoRa.cpp b/LoRa.cpp
index 5b805e6..8d3022b 100644
--- a/LoRa.cpp
+++ b/LoRa.cpp
@@ -78,6 +78,8 @@
#define REG_VERSION 0x42
#define REG_TXCO 0x4B
#define REG_PA_DAC 0x4D
+// These registers have different values in high and low frequency modes (flag 0x08 in mode)
+// We always stay in high frequency mode (flag is 0)
#define REG_AGC_REF 0x61
#define REG_AGC_THRESHOLD_1 0x62
#define REG_AGC_THRESHOLD_2 0x63
@@ -714,12 +716,13 @@ bool LoRaClass::resetModem()
REG_INVERT_IQ_2, 0x1d,
REG_TXCO, 0x09,
REG_PA_DAC, 0x84,
- REG_AGC_REF, 0x1C, // Datasheet says this defaults to 0x13, but dumping says 0x1c.
+ // These are the high frequency mode (mode flag 0x08 is 0) values
+ REG_AGC_REF, 0x1C,
REG_AGC_THRESHOLD_1, 0x0e,
REG_AGC_THRESHOLD_2, 0x5b,
- REG_AGC_THRESHOLD_3, 0xcc, // Datasheet says this defaults to 0xdb, but dumping says 0xcc.
+ REG_AGC_THRESHOLD_3, 0xcc,
REG_PLL, 0xd0,
- 0, 0;
+ 0, 0
};


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